1. Field of the Invention
The invention relates to a semiconductor memory and a method of fabricating the same. More particularly, the invention relates to an improvement for signal delay which occurs in a word line.
2. Description of the Related Art
In operation of a semiconductor memory, an address signal is decoded by a column address decoder to thereby select a certain word line, and a certain bit line is selected by a row address decoder. Then, through an input/output control circuit, data is written into or read from a memory cell disposed at an intersection of the thus selected word and bit lines. The data read out from a memory cell is amplified by a sense amplifier, and then output through the input/output control circuit.
The above mentioned word line is composed of relatively highly resistive material such as polysilicon of which a transistor gate is in general composed. In order to operate a semiconductor memory at higher speed and stably amplify bit line signals by means of a sense amplifier, it is necessary to minimize signal delay in a word line caused by wire resistance.
One of solutions to such signal delay is to form a second word line in parallel with a word line. The second word line is composed of material having a small wire resistance such as aluminum. The second word line is arranged to be in electrical connection with the word line through contacts, and a gate electrode is composed of highly resistive conductor such as polysilicon, thereby lowering a time constant of delay speed of signals to be transmitted to the word line.
For instance, in a high capacitance memory such as 16M DRAM and 64M DRAM, the number of transistor gates included in memory cells to be selected by a single word line reaches 4000 or 8000 or more. Hence, a word line cannot avoid to be lengthened. Thus, if a word line is composed of highly resistive material, signal delay in a word line is facilitated and accordingly it is impossible to operate a semiconductor memory at higher speed. In view of such a problem, an attempt has been made to carry out high-speed operation of a semiconductor memory by backing a word line with a second word line having a relatively low resistance to thereby lower a time constant of a word line with respect to transmission of drive signals.
In such an attempt, it is necessary to connect a word line with a second word line or a backing line. In a semiconductor memory, a connection called a contact is in general used. In a high capacitance semiconductor memory, a contact has to be minimized in size for minimizing an area of a chip. Accordingly, if fine dust is adhered to a surface of a semiconductor memory during a semiconductor memory fabrication process, a contact hole may be opened insufficiently. As a result, a word line is in insufficient connection with a second word line. As an alternative, even if a word line comes to connection with a second word line, such a connection is only through a hole resistance.
An example of the above mentioned second word line is described in Japanese Unexamined Patent Public Disclosure No. 63-48182. FIGS. 1A and 1B are cross-sectional views illustrating the second word line disclosed in No. 63-48182. FIG. 1A shows a positional relationship among a memory cell transistor, a word line and a second line as a backing line, and FIG. 1B shows that the word line is in connection with the second word line through a first aluminum wiring. As illustrated, on a P-type silicon substrate 301 is formed a memory circuit consisting of a polysilicon film and two aluminum wiring layers. The polysilicon film is patterned to form word lines 306, and a gate electrode and a capacity plate 305 of a transistor. A bit line is composed of a first aluminum wiring layer 309, and is in connection with a memory cell through an opening leading to a source/drain diffusion layer. A second aluminum wiring layers 311 are low resistive layers and serve as a backing layer for the word lines 306 composed of polysilicon. The second aluminum wiring layers 311 is in electrical connection with the first aluminum wiring 309, which is in connection with the word lines 306, through an opening.
The word lines 306 and the capacity plate 305 are covered with a first interlayer insulative film 308, and the bit line 309 composed of the first aluminum wiring layer extends over the first interlayer insulative film 308, and is connected to a source/drain region 307 composed of an n.sup.+ diffusion layer. Over the bit line 309 is deposited a second interlayer insulative film 310, on which extend the second aluminum wiring layers 311.
Through the first aluminum wirings 309, each of the word lines 306 are in electrical connection with each of the second aluminum wirings 311 serving as a low resistive backing wiring.
With reference to FIG. 2 illustrating a relationship among the word line, the backing wiring, and a plurality of memory cells of a semiconductor memory. A group of memory cells including a memory cell 204a are in electrical connection with a word line 201a composed of the first aluminum wirings 309. Over the word line 201a are arranged a group of backing wirings including a backing wiring 202a made of polysilicon and serving as a second wiring layer. Each of the backing wirings is in connection with an output terminal of a column decoder. As illustrated, the backing wiring 202a is in connection with an output terminal of a column decoder 205. The group of the backing wirings are in electrical connection with the group of the word lines through contacts at desired points. For instance, as illustrated in FIG. 2, the backing wiring 202a is in electrical connection with the word line 201a through a plurality of contacts (only 203a and 203b are illustrated).
In operation, for instance, when the content of the memory cell 204a is to be read out, the relatively low resistive backing wiring 202a is selected by the decoder 205, and then a word line drive signal .phi.2w is activated and transmitted to the backing wiring 202a. The word line drive signal .phi.2w is then transmitted to the relatively high resistive word line 201a through the contact 203a to thereby activate a gate of fie memory cell transistor 204a. The content of the memory cell 204a is read out and output onto a bit line selected by a row decoder (not illustrated), and then amplified by a sense amplifier.
The wire resistance of the word line 201a is in general about 10 to 100 times greater than the wire resistance of the backing wiring 202a. Hence, word-driving at higher speed is dependent on how frequently the contacts 203a, 203b,--are formed relative to the word line 201a and the backing wiring 202a. In the semiconductor memory illustrated in FIG. 2, a contact is arranged to drive six memory cells, namely, three by three at opposite ends thereof.
In the conventional semiconductor memory illustrated in FIGS. 1A, 1B and 2, if the contact 203a is broken for some reason and thus cannot transmit a signal therethrough, the activation of the memory cell 204a is carried out by a signal transmitted through the contact 203b. However, comparing the transmission speed of a signal transmitted through the contact 203b with the transmission speed of a signal transmitted through the contact 203a which is a proper route for transmitting a signal therethrough, the transmission speed through the contact 203b is made decreased due to the wire resistance and parasitic capacitance combined in a detour, that is, a difference in distance between a route from the decoder 205 to the memory cell 204a through the contact 203b and a route from the decoder 205 to the memory cell 204a through the contact 203a. The decreased transmission speed of a signal retards the activation of the memory cell 204a. In other words, a period of time from the activation of the word line drive signal .phi.2w to the activation of the memory cell 204a is made longer relative to an intended period of time due to the wire resistance of the parasitic capacitance of the word line 201a.
It is possible to design a semiconductor memory, which is intended to operate at higher speed, so that even if the contact defectiveness as mentioned above occurs, a bit line can be properly sense-amplified under certain conditions. Namely, a period of time from the activation of a word line drive signal .phi.2w to the commencement of sense-amplification of a bit line can be designed to be longer so as to compensate for the signal transmission delay in the word line which would be caused by the contact defectiveness. However, a semiconductor memory has to properly operate at ambient temperature ranging from 0 to 70 degrees centigrade. Polysilicon has the property that it comes to have higher wire resistance in lower temperature. Thus, in low ambient temperature, the transmission speed of a signal detoured through the contact 203b is further reduced, and accordingly the activation of the memory cell 204a is further retarded.
It is necessary to remove semiconductor memories having the contact defectiveness, even if such semiconductor memories electrically, properly operate at room temperature. For removal of such semiconductor memories, sorting memories with respect to electrical properties is most efficient and indispensable.